Thin Film Transistor Liquid Crystal Display (TFT-LCD) is an important flat panel display apparatus, and may be classified into a vertical electric field mode TFT-LCD and a horizontal electric field mode TFT-LCD according to the direction of electric field for driving the liquid crystal. The vertical electric field mode TFT-LCD requires to form a pixel electrode on an array substrate, and form a common electrode on a color filter substrate, for example a conventional TN mode TFT-LCD; and the horizontal electric field mode TFT-LCD requires to simultaneously form a pixel electrode and a common electrode on an array substrate, for example an ADS (Advanced Super Dimension Switch) mode TFT-LCD. ADSDS (ADS for short) is a general term for a core technology representing a wide view angle technology which is independently innovated by BOE. ADS refers to a core technology of plane electric field wide view angle-Advanced Super Dimension Switch, and the core technical characteristics are as follows: a multi-dimensional electric field is formed through an electric field generated at edges of slit electrodes in a plane and an electric field generated between the slit electrode layer and a plate electrode layer, so that liquid crystal molecules with all orientations between the slit electrodes and directly above the electrodes can rotate, thus the efficiency of the liquid crystal is enhanced and the transmittance efficiency is also increased. ADS technology can improve the image quality of TFT-LCD product, and has advantages such as high resolution, high transmissivity, low power consumption, wide view angle, high aperture ratio, low chromatic aberration and no push Mura. For various applications, modifications of ADS technology include a high transmissivity I-ADS technology, a high aperture ratio H-ADS technology and a high resolution S-ADS technology and the like.
FIG. 1 shows a structural diagram of a bottom gate type array substrate in a conventional ADS mode, and the array substrate may be manufactured through the following steps: forming a pattern including a common electrode 3 on a base substrate through a patterning process; forming a pattern including a gate 2 of a thin film transistor and a gate line 21 on the base substrate 1 subjected to the above step through a patterning process; forming a gate insulation layer 4 on the base substrate 1 subjected to the above step; forming a pattern including an active layer 6 on the base substrate 1 subjected to the above step through a patterning process; on the base substrate 1 subjected to the above step, forming an etch stop layer 7 and forming a source-drain contact region; on the base substrate 1 subjected to the above step, forming a pattern including a source 5-1, a drain 5-2 and a data line through a patterning process, wherein the source 5-1 and the drain 5-2 contact the active layer; forming a passivation layer 8 on the base substrate 1 subjected to the above step; and forming a pattern including a pixel electrode 9 on the base substrate 1 subjected to the above step through a patterning process. In manufacturing the ADS mode array substrate, the above five mask processes are generally used. However, the inventor finds that, as the mask is expensive, in manufacturing the array substrate by using five mask processes, the manufacturing procedure is complex and the cost is high.